1. Field of the Invention
The invention relates to a method of testing a multi-port memory, more particularly to a method of testing a multi-port memory using a sequence folding scheme to effectively reduce the testing time.
2. Description of the Related Art
System-on-chip (SOC) products generally incorporate hundreds of embedded memories, the size of which can occupy as much as 90% of the total chip area. Apart from memory capacity, the demand for data bandwidth in an SOC chip has increased as well. These led to the development of multi-port memories having a plurality of access ports that permit simultaneous access to memory cells. Multi-port memories are widely used in multiprocessor systems, network processors, graphic processing chips, devices with high performance requirements, etc., and are also found in data communication applications having different timing requirements. Therefore, in view of the increasing requirements for multi-port memories, technical problems of effective and rapid detection and diagnosis of defects in multi-port memories during the development phase, and of efficient testing during the mass production phase have become an important topic in the industry.
However, unlike a single-port memory, the multi-port memory provides parallel access paths that permit simultaneous access to different (or even the same) memory cells. In this sense, a multi-port memory differs very much from a single-port memory in architecture. Hence, an inter-port word line short or an inter-port bit line short in a multi-port memory will be more difficult to detect than damage in a conventional single-port memory. Accordingly, to promote efficiency in detecting damage in a multi-port memory, numerous test algorithms, including Zero-One, Checkerboard, CALPAT, Walking 1/0, Sliding Diagonal, Butterfly, and March algorithms, for a multi-port memory have been proposed in recent years. Among them, the March algorithm has proved to be superior in terms of testing efficiency. In accordance with different fault models of a multi-port memory, the basic March algorithm can be extended to result in other algorithms, such as MATS+, Marching 1/0, MATS++, March X, Match C+/C−, March A, March Y, March B, etc.
Taking the March C-algorithm as an example, the test pattern is: { (wa); ↑ (ra, wb); ↑ (rb, wa); ↓ (ra, wb) ↓ (rb, wa);  (ra)}, where a=0 or 1, b=ā (i.e., inverse of a), w represents a write operation, r represents a read operation,  represents that a memory write or read operation can be conducted in an ascending or descending order of memory addresses, ↑ represents that a memory write or read operation is conducted in the ascending order of the memory addresses, ↓ represents that a memory write or read operation is conducted in the descending order of the memory addresses, and ( ) indicates a test element that includes one or more memory operations, e.g., read a (ra), write b (wb), read b (rb), and write a (wa). Furthermore, the memory operations of a previous test element must be completed upon one of the memory cells (or memory addresses) before the memory operations of a succeeding test element can be performed upon said one of the memory cells (or memory addresses).
Therefore, assuming that a multi-port memory includes a pair of access ports A and B, when a test element ↑ (ra, wb) is to be executed, the prior art contemplates applying the consecutive memory operations (ra) and (wb) of the test element to each memory cell (or memory address) through the access port A, followed by applying the same memory operations (ra) and (wb) of the test element to each memory cell (or memory address) through the access port B. In this case, since each memory operation (ra) and (wb) requires at least one test clock cycle for completion, at least two test clock cycles are required when the memory operations of the test element ↑ (ra, wb) are conducted upon one of the memory cells (or memory addresses) through one of the access ports A or B. Since testing is actually conducted by treating the access ports A and B as individual ports, the test algorithm is executed twice such that one of the access ports A or B is idle when testing is conducted through the other of the access ports A or B.
In another conventional method of testing a multi-port memory, the consecutive memory operations (ra) and (wb) of the test element are applied to each memory cell (or memory address) by alternating between the access ports A and B. Particularly, the memory operation (ra) is applied through the access port A during a first test clock cycle, whereas the memory operation (wb) is applied through the access port B during a succeeding second test clock cycle. While two test clock cycles are still required when the memory operations of the test element ↑ (ra, wb) are conducted upon one of the memory cells (or memory addresses), it is no longer necessary to execute the test algorithm twice. However, one of the access ports A or B is still idle when testing is conducted through the other of the access ports A or B.
Since fault models of multi-port memories tend to be very complicated, corresponding complex algorithms are required for fault detection and testing. As a result, as capacities of multi-port memories become bigger, and as structures of multi-port memories grow in complexity, the test algorithms required also become more complicated, thereby resulting in a tremendous increase in testing time, which has an adverse affect on the testing efficiency of multi-port memories.